Drop Test. Drop Test Simulation o Effect of Thermal Agin Ford Packaging Drop Te Power Integrity Chip-P JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally.
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In order to cover a wide range of flip chips, the test vehicle used in this study is a daisy chain with a matrix of 5times5 and a pitch of mum. The results interpretation is assured by statistical distributions and failure analysis. It is a powerful tool because it is able to give a good qualitative understanding of physical aspects involved in drop test failures of the WL-CSP. The correlation between the dynamic simulation and experiment results is very good. The failures analysis revealed that the main failure modes in the component side are crack in the intermetallic layer and cracks in the passivation layer.
An other failure mode is detected at the board side but it can not be recorded as defect. The fact that cracking occurs predominantly at the component side is due to three factors: higher peeling stress S z at the component side, the brittleness of intermetallics and the strain-rate hardening of the bumps.
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BOARD LEVEL DROP TEST METHOD OF COMPONENTS FOR HANDHELD ELECTRONIC PRODUCTS